Latches
concept
A latch is a circuit which allows its output to be held even if the input is removed. For everything we've seen so far you need to constantly apply some logic level at the inputs and you'll get the corresponding logic level at the outputs.
With latches the story is different. A latch will hold its value ("latch" to a value) until you do something to change it (by changing its input and also sending it the signal to update its output).
In this way latches are the first example of a memory device, a latch will "store" a value at its output even if we stop applying the input that set that output.
S-R Latch
fact
A Set-Reset Latch (S-R Latch) is a circuit that allows you to set the latche's output to a 1 or a 0 by applying a momentary high at one of its two inputs, the set input or the reset input.
An S-R Latch is built like so:
The two outputs \(Q\) and \(\overline{Q}\) are always opposites (when one is a 1 the other is always a 0).
When a high value is applied to set (S), the output Q goes high (while \(\overline{Q}\) goes low)
When both S and R are held low the output doesn't change, only when one goes high does the latche's output get set (or reset).
The two outputs \(Q\) and \(\overline{Q}\) are always opposites (when one is a 1 the other is always a 0).
When a high value is applied to set (S), the output Q goes high (while \(\overline{Q}\) goes low)
When both S and R are held low the output doesn't change, only when one goes high does the latche's output get set (or reset).
We often use something called a timing diagram to describe these kinds of digital devices. A timing diagram shows how the output changes when the inputs are changed.
Below is a timing diagram for the S-R Latch:
Gated S-R Latch
fact
A gated S-R Latch is an S-R Latch with an additional "Enable" input, when enable is high the S and R inputs will work as normal, when enable is low S and R have no effect.
A Gated S-R Latch is built like so:
example
Determine the output \(Q\) for a gated S-R Latch whose inputs are:
When EN is 1 then a pulse of 1 on S makes Q go high and a pulse of 1 on R makes Q go low. Whenever EN is 0 S and R have absolutely no effect on Q and Q just remains at the same level until EN goes back to 1.Gated D Latch
fact
The gated D latch has two inputs, the D input and an enable input.
When enable is high the output Q will match the input D, when enable goes low Q (and \(\overline{Q}\)) will hold its value.
When enable is high the output Q will match the input D, when enable goes low Q (and \(\overline{Q}\)) will hold its value.
example
Determine the output \(Q\) for the Gated D Latched with inputs:
When EN is a 1 the output Q is just the input D. However when EN is 0 the output Q stays at whatever value it had until EN goes back to 1.
practice problems